Computer system employing an improved real time clock alarm

ABSTRACT

A set of I/O indexed configuration registers are provided within a real time clock circuit of a computer system to allow the storage of the day, month and century for an alarm activation event. The I/O indexed configuration registers that store the alarm year, the alarm month, and the alarm day information are shadowed with respect to the I/O indexed configuration registers that store the current year, month, and day information for the real time clock circuit. An additional configuration register mapped within the configuration space of the computer system is provided that stores a bit that controls whether the configuration registers for the current year, month, and day will be accessed during an I/O cycle to a predetermined address of the indexed configuration registers, or whether the configuration registers for the alarm year, alarm month, and alarm day will be accessed during an I/O cycle to the predetermined address. In accordance with the improved real time clock alarm, system software is not required to track the year, day, and month associated with a desired alarm event. In addition, additional I/O space and index space is not occupied as a result of the additional indexed configuration registers. Accordingly, broad system compatibility is maintained.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to computer systems and more particularly to realtime clock (RTC) alarm circuits employed within computer systems.

2. Description of the Relevant Art

In modern computer systems, a real time clock (RTC) circuit is typicallyemployed to keep track of the time of day. A typical RTC can beprogrammed to produce or generate an RTC alarm event at a designatedtime. The RTC alarm event may cause, for example, the assertion of aninterrupt signal to the microprocessor.

Within a typical model 80486-based system, a set of I/O indexedconfiguration registers are mapped at a pre-designated I/O region of thecomputer system to store the current time and date as well as the timeat which an RTC alarm event is desired. However, configuration registersare not allocated for storing the day, the month, or the year of adesired RTC alarm event. As a result, system software must be configuredto keep track of the particular day, month, and year for a desired RTCalarm event if such selectivity is desired. In other words, the RTCalarm for a model 80486 system will occur twice (or once) per day, andsystem software must keep track of each RTC alarm to determine whetherit is the designated day, month, and year for triggering a desiredsystem response.

An RTC alarm is typically employed within power managed portablecomputer systems that utilize suspend (i.e., power-down) and resumefeatures. Such computer systems can be programmed to suspend or resumeat a specific date and time. Since the RTC alarm event will occur onceor twice every 24 hours, the system management software must keep trackof the alarm events to determine the specific day, month, and year atwhich a particular RTC alarm event occurred. This adds to the systemoverhead and also degrades battery life since the computer system mustbe resumed to evaluate (via software) each alarm event. That is, if aspecific date is specified by the programmer to trigger a particularevent, the computer system software must turn on the computer system upto twice a day to determine whether the desired date has arrived.

A further complication is that for most computer systems, memory spaceand I/O space are distributed across several physical devices and areoften limited. Typical computer systems have undergone a complexevolutionary path with respect to the mapping of memory and I/O space inorder to maintain backwards compatibility with existing hardware andsoftware. As a result of this complex evolutionary path, the allocationof additional I/O index space for additional RTC alarm functions mayconflict with the predefined I/O index mapping of other I/O peripheraldevices. As a result, changes in the hardware (i.e., the number ofindexed configuration registers) associated with the RTC alarm to reducethe overhead of the system software could adversely affect the overallcompatibility of the computer system with other I/O peripherals.

SUMMARY OF THE INVENTION

The problems outlined above are in large part solved by a computersystem employing an improved real time clock alarm in accordance withthe present invention. In one embodiment, a set of I/O indexedconfiguration registers are provided within a real time clock circuit ofa computer system to allow the storage of the day, month and century foran alarm activation event. The I/O indexed configuration registers thatstore the alarm year, the alarm month, and the alarm day information areshadowed with respect to the I/O indexed configuration registers thatstore the current year, month, and day information for the real timeclock circuit. An additional configuration register mapped within theconfiguration space of the computer system is provided that stores a bitthat controls whether the configuration registers for the current year,month, and day will be accessed during an I/O cycle to a predeterminedaddress of the indexed configuration registers, or whether theconfiguration registers for the alarm year, alarm month, and alarm daywill be accessed during an I/0 cycle to the predetermined address. Inaccordance with the improved real time clock alarm, system software isnot required to track the year, day, and month associated with a desiredalarm event. In addition, additional I/O space and index space is notoccupied as a result of the additional indexed configuration registers.Accordingly, broad system compatibility is maintained.

Broadly speaking, the present invention contemplates a real time clockcircuit for a computer system comprising a first register for storing avalue indicative of the current time, a second register for storing avalue indicative of the current day, a third register for storing avalue indicative of a time for a desired RTC alarm event, and a fourthregister for storing a value indicative of a day for the desired RTCalarm event. The real time clock circuit further comprises an indexdecoder coupled to the first, the second, the third, and the fourthregisters, wherein the index decoder is capable of selecting at leastone of the registers depending upon an index value. An index register iscoupled to the index decoder for storing the index value. The real timeclock circuit finally comprises a configuration register for storing aconfiguration bit, wherein the configuration bit controls whether thethird register or the fourth register is enabled during a designated I/Ocycle.

The invention further contemplates a method for operating a real timeclock circuit within a computer system comprising the steps of setting aconfiguration bit of a configuration register in a first state to enablea first set of registers, storing a value indicative of the current timewithin a first register of the first set of registers, storing a valueindicative of the current day within a second register of the first setof registers, and storing a value indicative of a time for a desired RTCalarm event within a third register of the first set of registers. Themethod comprises the further steps of setting the configuration bit ofthe configuration register in a second state to enable a fourth registerwherein the fourth register is associated with an I/O index value whichis the same as an I/O index value associated with either the first ofthe second register, and storing a value indicative of a day for thedesired RTC alarm event into the fourth register.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent uponreading the following detailed description and upon reference to theaccompanying drawings in which:

FIG. 1 is a block diagram of a computer system employing an improvedreal time clock in accordance with the present invention.

FIG. 2 is a block diagram of a portion of the computer system whichillustrates clock control and comparator circuitry associated with thereal time clock of FIG. 1.

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof are shown by way ofexample in the drawings and will herein be described in detail. Itshould be understood, however, that the drawings and detaileddescription thereto are not intended to limit the invention to theparticular form disclosed, but on the contrary, the intention is tocover all modifications, equivalents and alternatives falling within thespirit and scope of the present invention as defined by the appendedclaims.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings, FIG. 1 is a block diagram of a computersystem 100 including a microprocessor (CPU) 102 coupled to a real timeclock (RTC) circuit 104 via a system bus 106. Microprocessor 102 is adata processing unit that implements a predetermined instruction set.Exemplary processing units include the models 8386 and 8486microprocessors, among others. System bus 106 is illustrative of, forexample, a PCI (Peripheral Connect Interface) bus. It is understood,however, that other bus standards such as the ISA (Industry StandardArchitecture) or EISA (Extended Industry Standard Architecture) busstandards could be alternatively employed.

Generally speaking, real time clock circuit 104 is provided for trackingthe current time. Real time clock 104 is also associated with an alarmmechanism that allows a programmer to set a time and date at which analarm event is desired. As will be appreciated by those skilled in theart, the occurrence of an RTC alarm may be used to control or activate avariety of system management functions such as power managementfunctions.

In its illustrated form, real time clock circuit 104 includes a cycledecoder 110 coupled to system bus 106 and a configuration register 112coupled to cycle decoder 110. An index register 114 is further coupledto cycle decoder 110. An index decoder 116 is coupled to index register114, and an AND gate 118 is coupled at respective input terminals toconfiguration register 112 and cycle decoder 110. A first set ofconfiguration registers 130A-130E and a second set of configurationregisters 132A-132C are further coupled to index decoder 116. Aninverter 134 is finally coupled to an output terminal of AND gate 118.

Configuration register 130A is provided for storing the current month,configuration register 130B is provided for storing the current day,configuration register 130C is provided for storing the current year,and configuration register 130D is provided for storing the currenttime. The values stored by configuration register 130A-130D arecontrolled by a clock control circuit (illustrated in FIG. 2).Configuration register 130E is finally provided for storing the time ofa desired alarm event.

Index register 114 is mapped at a predetermined I/O address of computersystem 100. In the preferred embodiment, index register 114 is mapped atthe I/O address 70:H. Index register 114 is provided for storing anindex value which points to one of the configuration registers130A-130E. Index decoder 116 receives the index value from indexregister 114 and asserts an enable signal at one of lines 140-144. Thus,index decoder 116 selects which of the configuration registers 130A-130Emay be accessed (i.e., either read or written) during an I/O cycle to asecond predetermined I/O address location referred to as the RTCconfiguration data register location. In one embodiment, the RTCconfiguration data register location is mapped at I/O address 71:H.

Configuration register 132A is provided for storing the month of thedesired alarm event, configuration register 132B is provided for storingthe day of the desired alarm event, and configuration register 132C isprovided for storing the year of the desired alarm event. Similar toconfiguration registers 130A-130C, configuration registers 132A-132C areselected by the signals at lines 142-144 from index decoder 116. In thepreferred embodiment, configuration registers 130A and 132A are selectedby index decoder 116 when a value of 07:H is stored within indexregister 114, configuration registers 130B and 132B are selected when avalue of 08:H is stored within index register 114, and configurationregisters 130C and 132C are selected when a value of 09:H is storedwithin index register 114. Configuration registers 130D and 130E arefinally selected by index decoder 116 when values of 0A:H and 0B:H arestored within index register 114.

Although configuration registers 130A and 132A are selected by the sameindex value (and configuration registers 130B, 132B and configurationregisters 130C, 132C are selected similarly), only one of the registersmay be enabled during a given cycle in accordance with a pair ofcomplementary enable signals at lines 150 and 152. When an I/O cycle isexecuted to the RTC configuration data register address, a bit 154within configuration register 112 controls which of the configurationregisters 130A-130E or 132A-132C are enabled via lines 150 and 152,respectively.

For example, consider a situation in which the current month, day, year,and time are stored within configuration registers 130A-130D,respectively. If the user desires a particular alarm event to occur at 2o'clock on Oct. 15, 1999, the real time clock 104 can be programmed inthe following manner. First, to set the alarm time, the bit 154 ofconfiguration register 112 must be low. This low value may be set bydefault, or may be caused by executing a cycle to the configurationspace of computer system 100 to which configuration register 112 ismapped. After properly setting the bit 154 of configuration register 112low, and index value of 0B:H must be written to index register 114 toselect the configuration register 130E. This is accomplished byexecuting an I/O write cycle to the I/O address of index register 114(which is, in the preferred embodiment, mapped at I/O address 70:H).Once configuration register 130E has been selected in accordance withthe index value of index register 114, an I/O write cycle may beexecuted on system bus 106 to store the alarm time data (i.e.,corresponding to 2 o'clock) within configuration register 130E. This isaccomplished by executing an I/O write cycle to the RTC configurationdata register address, which is, in the preferred embodiment, mapped ataddress 71:H. It is noted that during such and I/O cycle, cycle decoder110 drives the line 158 high, which causes the output of AND gate 118 togo high. Line 150 responsively goes low, and configuration register 130Eis thereby enabled. It is further noted that cycle decoder 110 generatesan appropriate read/write control signal which is provided to each ofthe configuration registers.

After the desired alarm time has been stored within configurationregister 130E, the desired alarm month, alarm day, and alarm year datamust be stored in turn within configuration registers 132A-132Crespectively. In order to enable configuration registers 132A-132C,however, the bit 154 of configuration register 112 must be set high.Similar to the previous description, the bit 154 of configurationregister 112 may be set by executing a write cycle to the configurationaddress to which configuration register 112 is mapped (note that theconfiguration space of computer system 100 is accessed by asserting thePCI signal IDSEL). Subsequently, an appropriate index value (i.e.,07:H-09:H) may be written into index register 114 to select one of theconfiguration registers 132A-132C, and an I/O write cycle to theconfiguration data register address (I/O address 71:H) may be executedto write the appropriate data into the selected configuration register132A-132C. Similar cycles may be initiated to write the remaining alarminformation into the remaining configuration registers 132A-132C.

It is noted that although configuration registers 130A and 132A areselected simultaneously by index decoder 116 (i.e., when the index valueis 07:H), only one of the configuration registers can be enabled bycycle decoder 110 at a given time in accordance with the enable signalsat lines 150 and 152. The same is true for configuration register 130B,132B and 130C, 132C.

Referring next to FIG. 2, a block diagram of another portion of realtime clock circuit 104 is illustrated. Circuit portions that correspondto those of FIG. 1 are numbered identically for simplicity and clarity.

FIG. 2 illustrates the clock control circuit 202 that controls thecurrent time and date within configuration registers 130A-130D. A set ofcomparators 204-207 are further provided for comparing the current timeand date information with the alarm time and date information (storedwithin configuration registers 130E and 132A-132C). An output of eachcomparator 204-207 is coupled to a respective input terminal of an ANDgate 206, which asserts an interrupt signal to microprocessor 102 highif the current time and date information matches the alarm time and dateinformation. In other words, the output of AND gate 206 triggers an RTCalarm event.

In accordance with the real time clock described above in conjunctionwith FIGS. 1 and 2, a real time clock alarm circuit is provided thatallows the setting of both the alarm time as well as the alarm date. Asa result, system software is not required to track the current date fora particular alarm event. System overhead is thereby minimized. Inaddition, since the indexed configuration registers that store the alarmmonth, alarm day, and alarm year information are shadowed with respectto the configuration registers that store the current date information,and are selected by the same I/O index values, additional indexed I/Ospace of the computer system 100 is not occupied. As a result, the realtime clock circuit will not present compatibility conflicts with otherI/O peripheral devices which may be incorporated within the computersystem.

Numerous variations and modifications will become apparent to thoseskilled in the art once the above disclosure is fully appreciated. Forexample, it is noted that although configuration register 112 is mappedwithin the configuration space of computer system 100, configurationregister 112 could alternatively be mapped within the I/O or memoryspace of computer system 100. In addition, it is noted that the dateinformation stored by the real time clock may comprise only dayinformation, or only month and day information, depending upon thedesired selectivity of the real time clock alarm circuit. It is intendedthat the following claims be interpreted to embrace all such variationsand modifications.

What is claimed is:
 1. A real time clock circuit for a computer systemcomprising:a first register for storing a value indicative of thecurrent time; a second register for storing a value indicative of thecurrent day; a third register for storing a value indicative of a timefor a desired RTC alarm event; a fourth register for storing a valueindicative of a day for said desired RTC alarm event; an index decodercoupled to said first, said second, said third, and said fourthregisters, wherein said index decoder is capable of selecting at leastone of said registers depending upon an index value; an index registercoupled to said index decoder for storing said index value; and aconfiguration register for storing a configuration bit, wherein saidconfiguration bit controls whether said third register or said fourthregister is enabled during a designated I/O cycle.
 2. The real timeclock circuit as recited in claim 1 wherein said configuration registeris mapped within a configuration space of said computer system.
 3. Thereal time clock circuit as recited in claim 1 wherein said index decoderselects both said third register and said fourth register when apredetermined index value is stored within said index register.
 4. Thereal time clock circuit as recited in claim 1 further comprising a cycledecoder coupled to said configuration register and to said indexregister, wherein said cycle decoder is for decoding cycles executed ona system bus of said computer system.
 5. The real time clock circuit asrecited in claim 4 wherein said cycle decoder is capable of causing datato be latched within said configuration register when a configurationcycle to a predetermined address is executed on said system bus.
 6. Thereal time clock circuit as recited in claim 4 wherein said cycle decoderis capable of causing data to be latched within said index register whenan I/O write cycle to a predetermined address is executed on said systembus.
 7. The real time clock circuit as recited in claim 4 wherein saidcycle decoder is capable of providing a write control signal to saidfirst, said second, said third, and said fourth registers when an I/Owrite cycle to a predetermined address is executed on said system bus.8. The real time clock circuit as recited in claim 7 wherein the writingof data into either said first, said second, said third, or said fourthregister is dependent upon which of said registers is selected by saidindex value and upon said configuration bit.
 9. The real time clockcircuit as recited in claim 1 further comprising a first comparatorcircuit coupled to said second register and said fourth register fordetermining whether said value indicative of said current day equalssaid value indicative of said day for said desired RTC alarm event. 10.The real time clock circuit as recited in claim 9 further comprising asecond comparator circuit coupled to said first register and to saidthird register and capable of determining whether said value indicativeof said current time equals said value indicative of said time for saiddesired RTC alarm event.
 11. The real time clock circuit as recited inclaim 10 further comprising a logic circuit capable of asserting an RTCalarm if said value indicative of said current time equals said valueindicative of said time for said desired RTC alarm event and if saidvalue indicative of said current day equals said value indicative ofsaid day for said desired RTC alarm event.
 12. The real time clockcircuit as recited in claim 11 wherein said assertion of said RTC alarmcauses an assertion of an interrupt signal to a microprocessor of saidcomputer system.
 13. The real time clock circuit as recited in claim 1further comprising:a fifth register for storing a vale indicative of thecurrent month; and a sixth register for storing a value indicative of amonth for said desired RTC alarm event; wherein said index decoder isfurther coupled to said fifth and sixth registers, and wherein saidindex decoder is capable of selecting said fifth and said sixth registerdepending upon said index value.
 14. The real time clock circuit asrecited in claim 13 wherein said configuration bit controls whether saidfifth register or said sixth register is enabled during anotherdesignated I/O cycle.
 15. A method for operating a real time clockcircuit within a computer system comprising the steps of:setting aconfiguration bit of a configuration register in a first state to enablea first set of registers; storing a value indicative of the current timewithin a first register of said first set of registers; storing a valueindicative of the current day within a second register of said first setof registers; storing a value indicative of a time for a desired RTCalarm event within a third register of said first set of registers;setting said configuration bit of said configuration register in asecond state to enable a fourth register, wherein said fourth registeris associated with an I/O index value which is the same as an I/O indexvalue associated with either said first of said second register; andstoring a value indicative of a day for said desired RTC alarm eventinto said fourth register.
 16. The method for operating a real timeclock circuit as recited in claim 15 comprising the further step ofstoring said I/O index value within an index register to select saidfirst register before said step of storing said value indicative of thecurrent time.
 17. The method for operating a real time clock circuit asrecited in claim 16 comprising the further step of storing said I/Oindex value into said index register for selecting said fourth registerbefore performing said step of storing said value indicative of a dayfor said desired RTC alarm event.
 18. The method for operating a realtime clock circuit as recited in claim 15 wherein said step of storingsaid value indicative of the current time is performed by executing anI/O cycle.
 19. The method for operating a real time clock circuit asrecited in claim 15 wherein said step of setting a configuration bit ofsaid configuration register in a second state is performed by executinga write cycle to a configuration state of said computer system.